1. Field of the Invention
The present invention relates to a PLL circuit and to a program for the PLL circuit.
2. Description of the Related Art
In a charge pump-type PLL circuit of the prior art, the output impedance value or fluctuation of output impedance value of PMOS and NMOS, which are the circuit elements that make up a charge pump circuit, generates differences between the charging current (hereinbelow abbreviated as “Isrc”) and the discharging current (hereinbelow abbreviated as “Isnk”), which should be the same values. A charge pump circuit of the prior art is therefore unable to maintain the output voltage within a desired range, and the output voltage may in some cases deviate from the locked voltage range. This is a flaw that degrades the performance of the PLL circuit.
The phase error that results from the charging current-discharging current error (Isrc-Isnk error) of a charge pump-type PLL circuit has been identified as a problem in the prior art, and various solutions have been proposed as a correction means, one example being the charge pump-type current correction circuit (CP circuit) of FIG. 1 described in JP-A-2003-87115 (hereinbelow referred to as “Patent Document 1”).
When using the UP pulse and DN pulse of a phase comparator to control the output voltage for charging and discharging the capacitance of LPF, the CP circuit of FIG. 1 of Patent Document 1 extracts the difference between the charging current and discharging current that is produced by divergence in the output impedance of PMOS and NMOS and corrects by means of a sense amplifier to eliminate the difference between the two currents. The output of this sense amplifier is fed back to the PMOS, whereby the output voltage is fixed or a prescribed voltage range is realized.
A PLL circuit of the prior art has a number of problems, the first problem being the existence of phase error in the PLL circuit. This problem occurs due to the occurrence of the Isrc-Isnk error of the charge pump circuit.
The second problem is the dependency of phase error upon processing, temperature, and the power supply voltage. This problem occurs because the Isrc-Isnk error of the charge pump circuit is dependent upon the charge pump input waveform, the process, the temperature, and the power supply voltage.
The CP circuit of FIG. 1 of Patent Document 1 is not directed to providing a solution for the Isrc-Isnk error that is free of dependency on the power supply voltage, the temperature, and the input waveform of the UP/DN signals that are applied as input to the charge pump circuit.